IOTA Crypto Core FPGA — Migrated to RISC-V

The full article was originally published by MicroEngineer on Medium. Read the full article here.

In case you missed the last report, click here

TL;DR: IOTA Crypto Core FPGA moved from Cortex ARM to RISC-V. RISC-V is much more open-source friendly (CPU-core MIT licensed), faster compared to Cortex M1 (e.g. hardware divider, I- and D-cache) and very flexible (extendable with plugins, custom instructions, …)

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Following is all about the small red IOTA Crypto Core FPGA module and its internal soft-cpu and hardware-accelerators.

You know, officially the funded IOTA Crypto Core project ended on 3rd September but the development continues … The focus shifted from building various base modules to further developing the FPGA module for secure standalone applications. This means you could use this module as the main-microcontroller in standalone applications and use the hardware acceleration for algorithms used in IOTA — on a module with 30x26mm size.

There is one issue I wasn’t very happy about … Perhaps you remember what I wrote about the ARM-Licensing issues in report 2 and in the last report:

What I would change, though, would definitely be to get rid of the Cortex M1 soft-cpu (ARM’s licensing is sub-optimal) and replace it by a (really) free RISC V. ARM gives the IP for the Cortex M1 cost-free but no part of their IP may be included in opensource code-repositories. So it was quite an effort to work-around the license — e.g. writing instructions how to download from the ARM website and to patch source-files afterwards for the ICCFPGA-project.

In the beginning, I started with the Cortex M1 because I was familiar with ARM microcontrollers, the toolchain, the debugging and so on … Because time was short it was the logic decision to use ARM on the FPGA-module. Changing to RISC-V at the project start would have brought a lot of unknowns which could have led to problems.

What is RISC-V

Wikipedia says about RISC-V:

RISC-V (pronounced “risk-five”) is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.

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