Qubic status update May 3rd 2019
The full article was originally published by Eric Hop on Medium. Read the full article here.
April was a month of consolidation, yet still saw some serious improvements as well. Especially by the end of the month we made some great strides forward and had several breakthroughs, which is why this is again a short update. There is a lot of work coming up, and time is better spent doing that.
We’ll go deeper into the nature of the breakthroughs in our next status update, when we have been able to explore and verify their nature.
This month was largely spent cleaning up the latest version and fixing some bugs. Lukas also updated the documentation files to reflect the latest changes.
All IXI modules now communicate with Ict and each other through the EEE model. Benoit has been working hard on the serialization.IXI, which now has its first stable incarnation. Samuel did more work on the graph.IXI and timestamping.IXI, and started on the weighing.IXI. Lukas created ec.IXI, which now contains the Economic Clustering component for Ict.
We have a new addition to the FPGA sub-team. Thomas Serbis (Serbeastio on Discord) has joined as full-time FPGA Design Engineer. This should finally give Donald some much-deserved relief.
For the rest there has been a lot of movement on the FPGA front. We have come to several important insights and are about to embark on a path that creates 3 (!!!) separate implementations of running trinary code on existing binary hardware. It will be interesting to compare these implementations to see which one performs best.
We released part 5 and part 6 in the series of articles that explore the depths of the Qubic Computation Model (QCM). Stay tuned for at least two more articles in this series. We also released an extremely simplified ELI9 article that explains things in layman terms.
The quality of the generated Abra code has been seriously improved by tuning some existing optimizations and adding a few new ones. For the rest a lot of time was spent experimenting with different looping constructs to simplify code that otherwise would have to resort to complex recursion.
These experiments are still ongoing. We’ve also started on a new and improved way of generating optimized Verilog code for FPGA. More on that next month.
We have been able to tap into two more community members that are helping us now with discussions about and contributions to the FPGA implementations.
First there is pmaxuw who had already been creating IOTA-specific FPGAs. And he in turn recommended and recruited Beeef, a seasoned FPGA design engineer whose knowledge, that he willingly shares, is so vast that it has leveled up the entire FPGA team.
There has also been a lot of activity in the #qubic channel on Discord this month with some very interesting discussions. Be sure to read up on them if you haven’t already.
As always, many thanks to everyone who participates there. It’s nice to see all the interest in what we are doing and the questions keep forcing us to come up with answers and fixes to things we might had otherwise missed. Many eyes on this project is how we manage to not lose sight of anything, no matter how trivial it may seem sometimes.
Until next month!